- 1 - e05729 this ic is esd sensitive device. s pecial handling precautions are required. sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or ot herwise under any patents or other right . application circuits shown, if any, are typical examples illu strating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXG1212UR high power 3p3t switch with logic control description this ic can be used in wireless communication systems, for example, cdma ev-do handsets. the ic has on-chip logic for operat ion with 3 cmos control inputs. the sony jphemt process is used for low insertion loss and on-chip logic circuit. (applications: antenna switch for cellular handsets, cdma, ev-do) features ? low insertion loss: 0.3db@900mhz ? 3 cmos compatible control line package small package size: 20-pin uqfn structure gaas jphemt mmic absolute maximum ratings (ta = 25 c) ? bias voltage v dd 7v ? control voltage vctl 5 v ? operating temperature topr ?35 to +85 c ? storage temperature tstg ?60 to +150 c ? rf input power pin = 37dbm
CXG1212UR - 2 - block diagram and recommended circuit when using this ic, the followi ng external components should be used: c rf : this capacitor is used for rf decoupling and must be used for all applications. cbypass: this capacitor is used for dc line filtering. truth table cbypass (100pf) 17 16 20 15 5 gnd 4 rf1 (cdma1) 3 gnd 1 gnd ctla ctlb ctlc v dd gnd rf5 (ext) 6 gnd rf3 (gps) gnd 9 gnd rf4 (main-ant) 13 gnd6 12 rf6 (sub-ant) 11 gnd c rf 14 gnd4 c rf 8 c rf c rf 2 c rf rf2 (cdma2) c rf 19 f10 10 7 18 f8 f9 f3 f12 f13 f11 f4 f2 f1 f5 f6 f7 state ctla ctlb ctlc mode on state f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 1 l l l cdma1 ext rf1 ? rf5 off on off off off off off off on on on off on 2l l h cdma1 ext cdma2 sub rf1 ? rf5 rf2 ? rf6 off on on off off off off off off on on off off 3 h l l cdma1 main rf1 ? rf4 on off off off off off off off on on off on on 4h l h cdma1 main cdma2 sub rf1 ? rf4 rf2 ? rf6 on off on off off off off off off on off on off 5 l h l gps ext rf3 ? rf5 off off off off off off on on on off on off on 6 l h h cdma2 ext rf2 ? rf5 off off off on off off off on off on on off on 7 h h l gps main rf3 ? rf4 off off off off on off off on on off off on on 8 h h h gps sub rf3 ? rf6 off off off off off on off on on off on on off
CXG1212UR - 3 - dc bias conditions (ta = 25 c) pin description item min. typ. max. unit vctl (h) 2.0 2.85 3.2 v vctl (l) 0 ? 0.5 v v dd 2.6 2.85 3.2 v pin no. symbol pin no. symbol 1gnd 11gnd 2 rf2 (cdma2) 12 rf6 (sub-ant) 3 gnd 13 gnd6 4 rf1 (cdma1) 14 gnd4 5 gnd 15 rf4 (main-ant) 6gnd 16gnd 7rf3 (gps) 17v dd 8 gnd 18 ctla 9 gnd 19 ctlb 10 rf5 (ext) 20 ctlc
CXG1212UR - 4 - electrical characteristics (ta = 25 c, v dd = 2.85v) *1 pin = 25dbm, 0/2.85v control, v dd = 2.85v, 900mhz *2 pin = 25dbm (900mhz) + 25dbm (901mhz), 0/2.85v control, v dd = 2.85v *3 pin = 25dbm, 0/2.85v control, v dd = 2.85v, 1.9ghz *4 pin = 25dbm (1.9ghz) + 25dbm (1.901ghz), 0/2.85v control, v dd = 2.85v item symbol condition min. typ. max. unit insertion loss il 900mhz 0.30 0.55 db 1.5ghz 0.40 0.65 db 1.9ghz 0.50 0.75 db isolation iso. 900mhz 23 30 db 1.5ghz 20 30 db 1.9ghz 18 25 db vswr vswr 50 ? 1.2 ? harmonics 2fo *1 ?75 ?60 dbc *3 ?75 ?60 dbc 3fo *1 ?75 ?60 dbc *3 ?75 ?60 dbc input ip3 iip3 *2 55 65 dbm *4 55 65 dbm 1db compression input power p1db v dd = 2.85v 32 dbm switching speed tsw 4 10 s bias current i dd v dd = 2.85v 270 450 a control current ictl vctl (h) = 2.85v 15 45 a
CXG1212UR - 5 - sony corporation package outline (unit: mm) pin 1 index c 0.1 s a-b 0.4 0.05 m s c c a-b s 0.05 s max0.02 + 0.09 20pin uqfn (plastic) 0.25 ? 0.03 + 0.09 0.14 ? 0.03 x 4 2.7 1 5 11 15 16 20 6 10 2.7 s 0.4 0.1 1.3 0.55 0.05 4-r0.3 0.26 a b 0.25 0.14 0.07 0.18 sony code eiaj code jedec code package material lead treatment lead material epoxy resin solder plating copper alloy 0.02g package structure uqfn-20p-01 package mass terminal section note:cutting burr of lead are 0.05mm max. solder plating lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec.
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